1. Field of the Invention
The present invention relates to a voltage detecting circuit and, more particularly, to a voltage detecting circuit for detecting the power-source voltage applied to the power-source terminal of a EPROM (Erasable Programmable ROM), in order to determine in which one of its operation modes the EPROM is set.
2. Description of the Related Art
Generally, EPROMs comprise floating gate type MOS transistors used as memory cell. To program the EPROM, that is, to write data into these memory cells, it is necessary to apply a voltage to the cells, which is higher than the voltage which is applied thereto to read data from the memory cells. Hence, two different power-source voltages must be externally applied to the EPROM. The EPROM, therefore, has two power-source terminals. An ordinary power-source voltage of 5 V is applied to the first power-source terminal at all times, and an ordinary power-source voltage of 5 V or a power-source voltage of 12.5 V is applied to the second power-source terminal only when required.
When the power-source voltage of 5 V is applied to the second power-source terminal, the EPROM is set in the data-reading mode. When the power-source voltage of 12.5 V is applied to the second power-source terminal, the EPROM is set in the programming mode. The voltage detecting circuit is incorporated in the EPROM. This circuit detects which power-source voltage, 5 V or 12.5 V, is applied to the second power-source terminal. From the voltage detected by the voltage detecting circuit, it is determined whether the EPROM should be set to the data-reading mode or the programming mode.
This detecting circuit detects whether the voltage applied to the second power-source terminal is higher than a predetermined value which is between 5 V and 12.5 V, or lower.
The conventional voltage detecting circuit includes a voltage-drop circuit and a CMOS inverter. The voltage detecting circuit detects a voltage by using, as a reference, the threshold voltage of the CMOS inverter.
The voltage-drop circuit is designed so as to lower the voltage applied to the second power-source terminal and being somewhere between 5 V and 12.5 V, to a value which is nearly equal to the threshold voltage of the CMOS inverter. More specifically, the voltage at the second power-source terminal of the EPROM is dropped by a predetermined constant value by means of the voltage-drop circuit. The voltage, thus dropped, is applied to the input terminal of the CMOS inverter. This voltage is higher than the threshold voltage of the CMOS inverter when the power-source voltage of 12.5 V is applied to the second power-source terminal of the EPROM, and is lower than the threshold voltage of the CMOS inverter when the power-source voltage of 5 V is applied to the second power-source terminal. Hence, the CMOS inverter generates an output signal at a logic "0" level when the power-source voltage of 12.5 V is applied to the second power-source terminal, and generates an output signal at a logic "1" level when the power-source voltage of 5 V is applied to the second power-source terminal. In accordance with the level of the output signal of the CMOS inverter, it is determined which power-source voltage, 5 V or 12.5 V, is applied to the second power-source terminal.
The detecting voltage of the detecting circuit change in accordance with the threshold voltage of the CMOS inverter.
The threshold voltage of the CMOS inverter changes in accordance with the drive-voltage which is applied to the first power-source terminal to drive the CMOS inverter.
To stabilize the threshold voltage of the CMOS inverter, the power-source voltage of 5 V applied to the first power-source terminal is used to drive the CMOS inverter. However, the voltage applied to the first power-source terminal varies by about 1 V in accordance with the operation mode, the data-reading mode or the programming mode. That is, a data-reading voltage of 6 V, which is one volt higher than the voltage applied to the first power-source terminal at all times must be applied to the first power-source terminal to set the EPROM in so-called "program verifying mode", whereby a reliable test is effect on the memory cells to determine whether or not correct data has been written into the memory cells.
It will now be explained why a reliable test can be effected.
The memory cells of the EPROM are floating-gate type transistors. Electrons are injected into the floating gate of any selected cell (i.e., transistor), thereby writing a data "0" into the cell. Then, the threshold voltage of the cell rises above the voltage applied to the first power-souce terminal. Any memory cell, the floating gate of which has no electrons injected into it, and the threshold voltage of which is lower than the voltage applied to the first power-source terminal, is regarded as storing a data "1". To read data from the memory cells, the voltage applied to the first power-source terminal is applied to the gates of the cells. Those cells storing data "0" are not turned on since their threshold voltage is higher than the power-source voltage. In contrast, those cells storing data "1" are turned on since their threshold voltage is lower than the power-source voltage. Hence, it is determined whether each cell stores a data "0" or a data "1", in accorance with whether the cell is turned on or off when the power-source voltage is applied to the cell.
As has been pointed out, the memory cell (i.e., the transistor) is turned off when its threshold voltage rises above the voltage applied to the first power-source terminal. The more electrons injected into the floating gate of the memory cell, and the higher the threshold voltage of the memory cell, the more reliable is the memory cell.
Therefore, in oder to make each memory cell sufficiently reliable, that is, in order to raise the threshold voltage of the cell, a voltage is applied to the first power-source terminal when the EPROM is set in the program verifying mode, which voltage is higher than when the EPROM is set in the data read mode. When the EPROM is set in the program verifying mode, the voltage applied to the first power-source terminal should better be as high as possible.
When the program-verifying voltage of 6 V is applied to the first power-source terminal, the threshold voltage of the CMOS inverter, which is driven by the voltage of 6 V, becomes higher than when the voltage of 5 V is applied to the first power-source terminal.
Since the threshold voltage of the CMOS inverter is higher when the EPROM is set in the programming mode than when the EPROM is set in the data read mode, the reference level for determining the output voltage of the voltage detecting circuit is also higher when the EPROM is set in the programming mode than when the EPROM is set in the data read mode.
When the EPROM is set in the data read mode, it is desirable that the reference voltage be high for the following reason. In the data read mode, the same voltage as is applied to the first power-source terminal i.e., 5 V, is applied also to the second power-source terminal. Noise may be generated in the second power-source terminal. If this is the case, the voltage at the second power-source terminal will rise above 5 V. If the reference level is lower than this risen voltage, the voltage detecting circuit will detect the noise, and the EPROM will be automatically set into the programming mode erroneously.
On the other hand, when the EPROM is set in the programming mode, it is desirable that the reference voltage be low to have a broad noise margin, for the following reason. If the threshold voltage of the transistor of the voltage detecting circuit is higher than the design value due to process errors, the reference voltage must be higher than the voltage applied to the second power-source terminal. In this case, the voltage detecting circuit may fail to detect that the voltage applied to the second power-source terminal has risen above 12.5 V. Further, when noise is generated in the second power-source terminal during the programming, whereby the voltage at this terminal falls below the reference voltage, then the voltage detetecting circuit will detects this voltage drop, thereby erronesouly setting the EPR0M into the data read mode.
Nonetheless, as has been pointed out, the reference voltage used in the conventional voltage detecting circuit is lower when the EPROM is set in the data read mode than when the EPROM is set in the programming mode.
If the reference voltage is set at a high value, it will have a noise margin broad enough for achieving correct reading of data. The voltage applied to the first power-source terminal is higher when the EPROM is set in the progrmming mode than when the EPROM is set in the data read mode. Therefore, the reference voltage must be even higher when the EPROM is set in the programming mode, and must have a narrower noise margin. Obviously, it is impossible with the conventional voltage detecting circuit to broaden both the noise margin for the data-reading operation and the noise margin for the programming operation.
Therefore, the conventional voltage detecting circuit can hardly determine correctly whether the power-source voltage applied to the second power-source terminal is 5 V or 12.5 V.